PWM_0_CTL_GENAUPD=PWM_0_CTL_GENAUPD_I, PWM_0_CTL_DBRISEUPD=PWM_0_CTL_DBRISEUPD_I, PWM_0_CTL_DBFALLUPD=PWM_0_CTL_DBFALLUPD_I, PWM_0_CTL_GENBUPD=PWM_0_CTL_GENBUPD_I, PWM_0_CTL_DBCTLUPD=PWM_0_CTL_DBCTLUPD_I
PWM0 Control
| PWM_0_CTL_ENABLE | PWM Block Enable |
| PWM_0_CTL_MODE | Counter Mode |
| PWM_0_CTL_DEBUG | Debug Mode |
| PWM_0_CTL_LOADUPD | Load Register Update Mode |
| PWM_0_CTL_CMPAUPD | Comparator A Update Mode |
| PWM_0_CTL_CMPBUPD | Comparator B Update Mode |
| PWM_0_CTL_GENAUPD | PWMnGENA Update Mode 0 (PWM_0_CTL_GENAUPD_I): Immediate 2 (PWM_0_CTL_GENAUPD_LS): Locally Synchronized 3 (PWM_0_CTL_GENAUPD_GS): Globally Synchronized |
| PWM_0_CTL_GENBUPD | PWMnGENB Update Mode 0 (PWM_0_CTL_GENBUPD_I): Immediate 2 (PWM_0_CTL_GENBUPD_LS): Locally Synchronized 3 (PWM_0_CTL_GENBUPD_GS): Globally Synchronized |
| PWM_0_CTL_DBCTLUPD | PWMnDBCTL Update Mode 0 (PWM_0_CTL_DBCTLUPD_I): Immediate 2 (PWM_0_CTL_DBCTLUPD_LS): Locally Synchronized 3 (PWM_0_CTL_DBCTLUPD_GS): Globally Synchronized |
| PWM_0_CTL_DBRISEUPD | PWMnDBRISE Update Mode 0 (PWM_0_CTL_DBRISEUPD_I): Immediate 2 (PWM_0_CTL_DBRISEUPD_LS): Locally Synchronized 3 (PWM_0_CTL_DBRISEUPD_GS): Globally Synchronized |
| PWM_0_CTL_DBFALLUPD | Specifies the update mode for the PWMnDBFALL register 0 (PWM_0_CTL_DBFALLUPD_I): Immediate 2 (PWM_0_CTL_DBFALLUPD_LS): Locally Synchronized 3 (PWM_0_CTL_DBFALLUPD_GS): Globally Synchronized |
| PWM_0_CTL_FLTSRC | Fault Condition Source |
| PWM_0_CTL_MINFLTPER | Minimum Fault Period |
| PWM_0_CTL_LATCH | Latch Fault Input |